Research
Power Management Integrated Circuit Design
Power management integrated circuits (PMIC) are critical for improving energy efficiency, reducing thermal dissipation, and extending battery life in mobile and internet-of-things (IoT) applications. Some of our past work includes:
Capless analog low-dropout regulators (LDO) and digital LDOs [US Patent 1], [US Patent 2], [ICECS'10], [Book]
Light-load efficient and wide-dynamic range DC-DC converters [MWSCAS'09, GoMACTech'11]
Ultra low-quiescent current analog IPs. [ICECS'11]
Currently, we are interested in
Hybrid DC-DC Converters amiable for Automotive (12V/48V) applications
Voltage Regulating Cable
Students: Nipun Kaushik.
Hardware Security of Integrated Circuits
Mathematically secure cryptographic algorithms may leak side-channel information when implemented on a chip. How to detect and defend side-channel attacks in a hardware and energy-efficient manner has attracted our interest.
Real-time power side-channel attack detection circuits. [ISCAS'21a], [ISCAS'21b], [MWSCAS'21]
We also want to secure Neural Networks against side-channel attacks and adversarial machine learning.
Students: Rowshon, Nipun, Christian, Aaron.
Analog VLSI Circuits Radiation Hardened by Design
Low Orbit Earth (LEO) and deep space present a very harsh environment for microelectronics to operate due to the "short-term" Single-Event Effects (SEE) and "long-term" Total Ionizing Dosage (TID). Our work seeks to Radiation Harden Analog / Mixed-Signal circuit building blocks By Design (RHBD) instead of relying on specialized processes.
RHBD Comparators for Successive Approximation Register (SAR) ADCs
Student: Andrew Ash. (Image credit: NASA)
600 square feet of dedicated space for IC testing. ESD flooring installed in 2019, which prevents unintentionally "zapping" ICs. (Nov, 2019)
Electronics Design Automation (EDA)
Our laboratory is equipped with industry-standard IC design software and EDA suits, including:
Cadence Analog Design Environment (IC6.1.7-64b)
Mentor Graphics Calibre: Layout design (DRC), verification (LVS), and parasitic extraction (PEX)
Process Design Kit (PDK)
We have signed non-disclosure agreements (NDA) with TSMC and UMC to use their selective technologies for research prototyping.
TSMC: 65nm RF/MS/GP CMOS. IP available: Standard cell libraries, I/O, ESD
UMC: 130nm CMOS.
TSMC: 180nm Bipolar/CMOS/DMOS. IP available: Standard cell libraries, I/O, ESD
Laboratory Space and Equipment
Room: ATRC 235 (600 square feet)
Purpose: Dedicated space for IC test and measurement. ESD protected.
Chips Gallery
Dual-mode LDO
UMC 0.13 um CMOS (2020)
Switched-cap PSCA detector
TSMC 65 nm CMOS (2021)
Revised PSCA detector
TSMC 65 nm CMOS (2022)
Sponsors
A list of our current and past sponsors:
